The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs, the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal or by enlarging or constricting the conducting channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor.
The space between the two diffusion areas is called the “channel”. The channel is where current flows, between the source (S) and the drain (D). A schematic symbol for an n-channel MOSFET appears to the left of FIG. 1.
A thin dielectric layer is disposed on the substrate above the channel, and a “gate” structure (G) is disposed over the dielectric layer, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.)
Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded or biased at a desired voltage depending on applications.
Generally, when there is no voltage applied to the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity, plus or minus) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors are used, and are often paired with one another.
While particular n- and p-type dopants may described herein according to NMOS technology, it is to be appreciated that one or more aspects of the present invention are equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type dopants).
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching.
DRAM and eDRAM
Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to static random access memory (SRAM) and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to (typically) six transistors in SRAM. This allows DRAM to reach very high density. Like SRAM, DRAM is in the class of volatile memory devices, since it loses its data when the power supply is removed. In general, a DRAM cell comprises an access transistor (or memory cell), and a storage capacitor.
Embedded DRAM (eDRAM) is a capacitor-based dynamic random access memory usually integrated on the same die or in the same package as the main ASIC or processor, as opposed to external DRAM modules and transistor-based SRAM typically used for caches.
Embedded dynamic random access memory (eDRAM) has its memory cells and its logic cells formed on a single silicon chip. eDRAM is capable of transferring large quantity of data at a very high speed. Due to its high memory capacity and speed, eDRAM has been used inside high volume processing circuits, an example of which is a graphic processor. A complete embedded DRAM includes logic circuits, a transfer field effect transistor (transfer FET) and a capacitor coupled to the transfer FET. The transfer FET actually acts as a switch between the lower electrode of the capacitor and a bit line. Therefore, data within the capacitor can be written in or read out.
FIG. 2 illustrates an exemplary eDRAM cell 200 of the prior art. On the right is a DRAM cell 210, and on the left is a logic transistor 220. Related contacts and interconnects for wiring the logic transistor 220 to the DRAM cell 210 are omitted, for illustrative clarity.
The DRAM cells and the logic circuits of an embedded DRAM are formed above a substrate 202 on a single chip. Normally, the substrate is a P-type silicon substrate. In general, device isolation regions 204 are formed using a local oxidation of silicon (LOCOS) method.
Alternatively, devices can be isolated by forming shallow trench isolation (STI) structures. Shallow trench isolation structures are formed by first etching out a trench, and then depositing oxide material into the trench using a chemical vapor deposition method.
The DRAM cell 210 and the logic transistor 220 are both essentially FETs, each comprising source/drain diffusions in the substrate 202 and a gate stack on the substrate between the source/drain diffusions.
In general, the logic circuit area and the memory cell area in an embedded DRAM have different gate structures. The gate of a DRAM cell normally comprises a tungsten silicide layer and a polysilicon layer, while the gate in a logic circuit area comprises a metal silicide layer and a polysilicon layer.
The DRAM cell 210 has a gate stack 212 comprising (from bottom, up) a gate oxide layer, a polysilicon layer, a metallic silicide layer and a silicon nitride gate cap layer. The DRAM cell 210 has source/drain regions 214. Sidewall spacers 216 may be formed on the gate stack 212. The memory transistor 210 is typically an NFET, and may also be referred to as a memory transistor, or an Array NFET.
The logic transistor 220 has a gate stack 222 comprising (from bottom, up) a gate oxide layer, a polysilicon layer, a metallic silicide layer and a silicon nitride gate cap layer. The logic transistor 220 has source/drain regions 224. Sidewall spacers 226 may be formed on the gate stack 222. The logic transistor 220 may have a self-aligned silicide layer 228.
The single logic transistor 220 shown is exemplary of either PFET or NFET, such as may both be used in CMOS logic circuitry for operating the DRAM cell 210.
A thick dielectric layer 230 is formed over the substrate 202, and then a contact opening 232 is formed in the dielectric layer 230 exposing one of the source/drain regions 214 of the memory transistor 210. Next, a conductive layer 234, a dielectric thin film 236 and another conductive layer 238 are sequentially formed above the substrate 202. Hence, a capacitor 240 having electrical connection with the source/drain region 214 of the memory transistor 210 is formed.